The present invention relates to increasing the quality and desired properties of semiconductor materials used in electronic devices, particularly power electronic devices. In particular, the invention relates to an improved process for minimizing crystal defects in silicon carbide, and the resulting improved structures and devices. The present invention is related to the subject matter disclosed and claimed in co-pending and commonly assigned application Ser. No. 10/046,346; filed Oct. 26, 2001 and now published as No. 2003-0080842 A1; the contents of which are incorporated entirely herein by reference.
Silicon Carbide
Silicon carbide (SiC) has emerged over the last two decades as an appropriate candidate semiconductor material that offers a number of advantages over both silicon and gallium arsenide. In particular, silicon carbide has a wide bandgap, a high breakdown electric field, a high thermal conductivity, a high saturated electron drift velocity, and is physically extremely robust. In particular, silicon carbide has an extremely high melting point and is one of the hardest known materials in the world.
Because of its physical properties, however, silicon carbide is also relatively difficult to produce. Because silicon carbide can grow in many polytypes, it is difficult to grow into large single crystals. The high temperatures required to grow silicon carbide also make control of impurity levels (including doping) relatively difficult, and likewise raise difficulties in the production of thin films (e.g. epitaxial layers). Because of its hardness, the traditional steps of slicing and polishing semiconductor wafers are more difficult with silicon carbide. Similarly, its resistance to chemical attack make it difficult to etch in conventional fashion.
In particular, silicon carbide can form over 150 polytypes, many of which are separated by relatively small thermodynamic differences. As a result, growing single crystal substrates and high quality epitaxial layers (“epilayers”) in silicon carbide has been, and remains, a difficult task.
Nevertheless, based on a great deal of research and discovery in this particular field, including that carried out by the assignee of the present invention, a number of advances have been made in the growth of silicon carbide and its fabrication into useful devices. Accordingly, commercial devices are now available that incorporate silicon carbide to produce blue and green light emitting diodes, as a substrate for other useful semiconductors such as the Group III nitrides, for high-power radio frequency (RF) and microwave applications, and for other high-power, high-voltage applications.
As the success of silicon-carbide technology has increased the availability of certain SiC-based devices, particular aspects of those devices have become more apparent. In particular, it has been observed that the forward voltage (also referred to as “forward bias”) of silicon carbide-based bipolar devices tends to increase noticeably during operation of those devices. For a number of reasons, such functional problems in semiconductor devices can often result from defects in the crystal structure of the material from which the devices are formed.
Crystallographic Defects
At the most basic level, structural crystallographic defects fall into four categories: point defects, line defects, planar defects and three dimensional defects. Point defects include vacancies, line defects include dislocations, planar defects include stacking faults and three-dimensional defects include polytype inclusions.
A dislocation is a kind of structural imperfection that extends for many unit cell lengths throughout a crystal. A more definite description of dislocation classifies them as screw and edge dislocations. As recognized by those persons skilled in this art, a symmetrical path followed from atom to atom (or from ion to ion) in a real crystal that returns upon itself, it is referred to as a Burgers circuit. If the same path in the lattice that typifies the structure does not return upon itself, so that the beginning and end do not lie on the same atom, then the Burgers circuit encloses one or more dislocations. The vector that completes the closed circuit in the lattice is referred to as the Burgers vector and measures the magnitude and direction of the dislocation.
If the Burgers vector is parallel to the line that locates the dislocation, the defect is referred to as a screw dislocation. Alternatively, if the Burgers vector is perpendicular to the dislocation, it is referred to as an edge dislocation. The simplest version of an edge dislocation is an incomplete plane of atoms or ions interleaved between two normal planes in a manner somewhat analogous to an extra card inserted halfway into a deck. On one side of the dislocation line, the planes separate to make room for the extra layer; on the other side the planes compress due to the absent layer.
Screw dislocations are not necessarily disadvantageous and, in fact, can be particularly important for the growth of a crystal face. A screw dislocation always presents one edge that is one or a few atoms high. At this edge, continued growth of the crystal is relatively easy. Dislocations, however, allow plastic flow to occur in a crystal relatively easily. In a limited region, the dislocation line created by the dislocation may be almost a straight line. Any plane that contains the Burgers vector and a segment of the dislocation line is referred to as a “slipped plane”. The edge dislocation moves relatively easily through the crystal because motion in the slipped plane involves only a slight displacement of the structural elements. Stated differently, the slipped planes provide a low-energy intermediate state by which a crystal can be reorganized.
Defects in Silicon Carbide
In silicon carbide power devices, the availability of such relatively low-energy intermediate state encourages faults to continue to grow as the operation of the device provides the relatively small amount of energy necessary for the crystal reorganization.
Commercial quality SiC wafers and epilayers include both screw and edge dislocations. These dislocations can be further grouped by their alignment within the crystal. Those dislocations that propagate along the c-axis are called threading dislocations, while dislocations that lie within the c-plane are termed basal plane dislocations. In general, in SiC, it is energetically favorable that basal plane dislocations preferentially decompose into partial dislocations via the mechanism described below:⅓<11-20>→⅓<10-10>+⅓<01-10>  Equation 1
The above decomposition reaction describes the decomposition of a basal plane dislocation into two Shockley partial dislocations. The line defects generated during the above decomposition will bound a planar stacking fault defect. In fact, partial dislocations will bind the entire perimeter of the stacking fault unless the stacking fault reaches a free surface. This stacking fault will be electrically active in bipolar devices and during forward operation, the electron-hole plasma will be reduced in the vicinity of the stacking fault. The reduced plasma density will increase the forward voltage of the device. A further complication is that through dislocation enhanced dislocation glide, the stacking fault may continue to expand during forward operation of the device. This behavior is a substantial barrier to device exploitation because it results in devices with functional properties that can change unpredictably during operation.
Stated differently, the application of electric current through a silicon carbide bipolar device tends to initiate or propagate (or both) changes in the crystal structure. As noted above, many SiC polytypes are in close thermodynamic proximity, and solid phase transformations are quite possible. When the stacking faults progress too extensively, they tend to cause the forward voltage to increase in an undesirable manner that can prevent the device from operating as precisely as required or desired in many applications.
In some conventions, dislocation density is described by centimeters of dislocation length per cubic centimeter of material, and thus report dislocation density units of per square centimeter (cm−2). In another convention (and as used herein) the off-axis orientation of 4H-SiC substrates for SiC epilayer growth and the common etch technique used to detect dislocations make it more convenient to use etch pit density (also in the units of cm−2), to describe dislocation densities in SiC. Those of skill in this art will thus recognize that for a given dislocation density expressed as cm/cm3, one could get a very different dislocation pit density when expressed as pits/cm2 depending on the typical dislocation configuration and the off-axis angle of the substrate. Therefore, although the two numbers will have the same net units (cm−2), they do not necessarily indicate the same actual dislocation density. For the sake of clarity and consistency, in this disclosure, dislocation density will only be described as the density of specific pits delineated on an etched epi-surface of a silicon face prepared, 8° off-axis (0001) oriented substrate.
Present commercially available 4H-SiC substrates have approximately 1E3 to 1E5 (103–105) dislocations per cm2 by the convention used herein. This includes threading screw and edge dislocations, micropipes and basal plane dislocations. FIG. 1 is a micrograph of KOH-etched epilayer surface revealing various common types of dislocation pits (the exact nature of which are set forth in the Detailed Description). All types of dislocations can impact device performance, but the basal plane dislocation is particularly implicated as being the prevalent nucleation site of the stacking faults that cause Vf drift.
In turn, defects in the substrate are often replicated in epitaxial layers grown on such substrates, thus making substrate crystal quality an important factor with respect to the quality and performance of resulting devices.
Conventional substrate preparation and epilayer growth practices will fairly effectively reduce the density of basal plane dislocations from 1E3–1E4 cm−2 in the substrate to about 400 cm−2 in the epilayer. This reduction in dislocation density is accomplished via changes in both the substrate preparation and the epilayer growth operations.
Because SiC is a very hard material, preparing a typical substrate requires fairly aggressive sawing, lapping and polishing operations. These steps all generate subsurface damage including enormous numbers of dislocations, including basal plane dislocations. To remove this damaged region, in practice, a less aggressive final preparation, such as chemical mechanical polishing (CMP) or a dry etch is employed after wafer shaping to remove subsurface damage. The inventors herein have observed, however, that in many cases sub-surface damage propagates several microns beyond the depth removed by such conventional final surface preparation. In particular, and without wishing to be bound by any particular theory, it is hypothesized (but not yet confirmed) that damage from the sawing operation is the predominant cause of the residual damage.
Accordingly, continued improvement in the structure and operation of SiC-based bipolar devices will require continued improvements in the underlying substrates and their crystal structures.